FPGA Hierarchical ALU & 7-Segment Display Controller

BOARDArtix-7 Basys3LANGUAGEVHDLTOOLCHAINXilinx Vivado 2024.2DEBUGILA

Hardware — Basys3 FPGA

Overview

Designed and implemented a 10-bit synchronous up/down counter in VHDL on an Artix-7 Basys3, integrating four modular subcomponents into a synthesized top-level architecture. The counter operates over a 0-to-1000 range, with each clock pulse triggered manually via the debounced center push button (BTNC). Direction (SW13), synchronous preset from SW0–SW9 (SW14), and asynchronous reset (SW15) are all switch-controlled. The binary output is converted to four-digit BCD by a standalone converter, then displayed on the 7-segment array via time-division multiplexing.

Implementation

Debouncer16-bit shift register clocked at 100MHz; output changes state only on all-high or all-low shift register, suppressing contact bounce on BTNC

Counter10-bit synchronous design with async reset priority, synchronous preset with overflow clamping to 1000, and up/down wraparound logic

BCD ConverterInteger division and modulo on CONV_INTEGER output; results packed into 16-bit BCD vector

SSD Driver20-bit free-running counter; top 2 bits select active digit and anode; 100MHz refresh

VerificationEach submodule verified with dedicated testbenches (signal assertions, waveform inspection) before top-level integration in Vivado

Footprint117 / 20,800 Artix-7 logic slices utilized post-synthesis

View Code on GitHub