10-bit Synchronous Up/Down Counter

This project involved designing and simulating a 10-bit synchronous up/down counter entirely in VHDL, implementing logic on the Basys3 FPGA platform. The overarching goal was to deepen understanding of sequential logic and state management while managing real physical button inputs (debouncing).

The system reads from onboard Basys3 switches to establish counting bounds (0 to 1000). A primary clock divider module scales down the 100MHz onboard clock for human-readable counting delays, and a debouncer circuit ensures that manual button presses correctly increment or decrement the state without ghost inputs.

Managing clock domains and resolving race conditions during synchronous updates was the primary challenge. Writing testbenches before deploying to the physical board proved crucial in isolating logic errors from hardware mapping issues.